c++ - Conditional expression in Makefile -

i know can use if statements following in makefiles:

foo: $(objects) ifeq ($(cc),gcc)         $(cc) -o foo $(objects) $(libs_for_gcc) else         $(cc) -o foo $(objects) $(normal_libs) endif 

is there way conditional replacement possibly ternary type operator.

(condition?$(cc):$(cc2)) -o foo $(objects) $(libs_for_gcc)   

and if there isn't idiomatic way achieve example

i added c++ tag because question had 7 views , figured used c++ might know answer,i know isn't strictly c++ question(though planning compile c++ it)

edit: looks there if function using syntax
$(if condition,then-part[,else-part])
i'm still little confused on how works though

the $(if ...) function can serve ternary operator, you've discovered. real question is, how conditionals (true vs. false) work in gnu make? in gnu make anyplace condition (boolean expression) needed, empty string considered false , other value considered true.

so, test whether $(cc) string gcc, you'll need use function return empty value when isn't, , non-empty value when is.

typically filter , filter-out functions used this. unfortunately it's easiest use these in such way "not equal" result; in other words, using these functions it's simpler accurately generate non-empty string (true) if string not gcc, , empty string (false) if value is gcc. example:

$(if $(filter-out gcc,$(cc)),$(info not gcc),$(info gcc))