how does u-boot maps peripheral memory? -

i confused how registers(for ex: uart controller) mapped in u-boot? memory mapped in ddr? if yes how? if not meaning of "peripheral addresses memory mapped" in u-boot?

welcome stackoverflow.

the registers mapped ram memory address space @ hardware level using different type of interconnects in soc. e.g lets take example of omap 35x series , see how uart registers mapped ram memory address space of soc , how may access them in u-boot.

in technical reference manual omap 35x, table 2-3. l4-core memory space mapping, see base address uart1 0x4806a000 , size (of ram occupies) 4kb.

it means registers uart1 mapped ram memory space in 4kb region starting @ address.

to access register of uart1, need know offset base address actual address. these offsets can found in table 17-39 uart irda cir register summary.

once know actual address make pointer register using

unsigned int * (base_address + offset) 

once have pointer can de-reference read/write register. e.g

to read register in variable 'x' use:

unsigned int x; x = *(unsigned int * (base_address + offset)); 

writing register similar

*(unsigned int *(base_address + offset)) = some_value; 

to better understanding of how memory mapping implemented @ hardware level, skim through chapter 2, 'memory mapping', of trm.